產業新訊
Realtek Semiconductor Corp. - Senior Design Verification Engineer
IC設計
【Company Name】
Realtek Semiconductor Corp.
Realtek Semiconductor Corp.
【Job Position】
Senior Design Verification Engineer
Senior Design Verification Engineer
【Job Specification】
- Responsibility for test plans, test bench documentation and implementation.
- Use System Verilog language, SVA and UVM methodology for block and top level verification.
- Apply formal property checking/formal verification methodologies
- Understanding of the fundamentals of computer architecture
【Job Requirements】
- MS Degree or above in Electrical, Electronics or Computer Engineering
- Familiar with System Verilog, SVA, Perl, CRV, VMM/UVM Methodology
- Familiar with EDA Tools such as Formal Verification Tool (Cadence Jasper, Synopsys Magellan)
- Good analytical problems solving skills
- Good C/C++ Programming skills
- Good verbal and written communication skills
- Self-motivated and possess team working skills5 years of working experience
【Job Location】
Hsinchu, Taiwan
Hsinchu, Taiwan
Date：2019/08/22